A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements

M. Rahimi | M.B. Ghaznavi-Ghoushchi

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URL :   http://research.shahed.ac.ir/WSR/WebPages/Report/PaperView.aspx?PaperID=116460
Date :  2019/04/19
Publish in :    Microelectronics Journal
DOI :  https://doi.org/10.1016/j.mejo.2019.04.009
Link :  http://dx.doi.org/10.1016/j.mejo.2019.04.009
Keywords :low-power, binary, inter-stage, binary, power-delay, improved, elements

Abstract :

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A new comparator based on the parallel prefix (PP) tree is presented. The improvement is utilized in both of algorithmic-level and cell-elements. First the PP algorithm of comparator is improved and then a novel “XNOR-AND” circuit is presented to use in proposed comparator. According to modified PP, two comparators are presented with similar comparator algorithm and different circuits in pre-encoder steps. The pre-layout and post-layout simulations of all circuits are performed in 65 nm and 180 nm standard CMOS technologies. Simulations of 16, 32 and 64-bit comparators in TT-corner of 180 nm show that the improvement of PDP of proposed1(proposed2) than conventional comparator are 35.62(51.23), 35.25(49.80) and 31.54(45.37), respectively. Also, the second proposed comparator circuit is investigated in Arithmetic Logic Unit (ALU). According to the simulation results, the improvement of PDP of ALU with proposed2 comparator than ALU with conventional comparator in 180 nm standard CMOS technology is 14.62.