A new parallel prefix adder structure with efficient critical delay path and gradded bits efficiency in CMOS 90nm technology

H. Moqadasi | M.B. Ghaznavi-Ghoushchi

---

URL :   http://research.shahed.ac.ir/WSR/WebPages/Report/PaperView.aspx?PaperID=30932
Date :  2015/05/14
Publish in :    بيست و سومين کنفرانس برق ايران
DOI :  https://doi.org/10.1109/iraniancee.2015.7146426
Link :  http://dx.doi.org/10.1109/IranianCEE.2015.7146426
Keywords :prefix, adder, critical, efficiency, CMOS, technology

Abstract :

---

http://dx.doi.org/10.1109/IranianCEE.2015.7146426