Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping

S. Rahmani | M.B. Ghaznavi-Ghoushchi

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URL :   http://research.shahed.ac.ir/WSR/WebPages/Report/PaperView.aspx?PaperID=64146
Date :  2017/10/03
Publish in :    Analog Integrated Circuits and Signal Processing
DOI :  https://doi.org/10.1007/s10470-017-1048-6
Link :  http://dx.doi.org/10.1007/s10470-017-1048-6
Keywords :double-tail, comparator, isomorphic, latch-preamplifier, bootstrapping

Abstract :

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Analog comparators are the basic circuit elements in analog to digital converters. In this paper, we present a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping. We used NAND gates because of its higher speed than the NOR gate, as SR-NAND-latch in second stage. The first stage is composed of two parts, preamplifier and voltage boosting block. Preamplifier utilized in a structure similar to latch, and voltages boosting increases the effective supply voltage in clock transition times, results in reduced delay. This results in a desirable speed at lower supply with reduced power consumption. The presented comparator is designed and simulated in both of 0.18-μm and 65-nm CMOS technologies. Simulation results in 0.18-μm show delay of proposed comparator reduced about 35 than conventional comparator. The proposed comparator operates correctly by 2.8 GHz at 1.1 V supply voltage with only 1.3 mW power. The simulation results in 65-nm CMOS technology show that delay and power consumption of isomorphic latch-preamplifier have significant reduction than the results in 180-nm. The proposed comparator is well-suited for mix-signal applications and SAR-ADC.