An output node split CMOS logic for high-performance and large capacitive-load driving scenarios

M. Rafiee | M.B. Ghaznavi-Ghoushchi

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URL :   http://research.shahed.ac.ir/WSR/WebPages/Report/PaperView.aspx?PaperID=84629
Date :  2018/02/01
Publish in :    Microelectronics Journal
DOI :  https://doi.org/10.1016/j.mejo.2017.12.010
Link :  https://doi.org/10.1016/j.mejo.2017.12.010
Keywords :split, CMOS, logic, high-performance, large

Abstract :

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In this paper, a new logic with split pull-up (PUN) and pull-down (PDN) networks of static CMOS is presented. The isolation is performed through a push-pull stage and an inner-feedback-interface. This causes two separated outputs of PUN/PDN to have the same voltage in identical evaluating points. Therefore, delay of proposed logic is less than CMOS. Maximum allowable load capacitance of proposed logic is increased. Adaptive-Body-Biasing (ABB) is used during the run-time to change the transistors effective-threshold-voltage in tradeoff for power and delay. To show the effectiveness of the new logic, an 8-bit Ripple-Carry Adder (RCA), an 8-bit Wallace multiplier and a 16-bit Carry-Look-Ahead Adder (CLA) are implemented and evaluated against, pseudo-static 1 and static CMOS logics on 65 nm standard CMOS technology. Simulations show that proposed logic is 15 and 35 faster than CMOS and pseudo-static, respectively. The proposed logic comes with 28 speedup over CMOS in low-voltage region due to fewer series stages between supply voltage and ground nodes.